1. Field of the Invention
The present invention relates to layout design of a semiconductor device and post-chemical mechanical planarization (CMP) planarity.
2. Description of the Related Art
Recently, as semiconductor devices become smaller with multilayer wiring, a flat topography of the respective layers has become desirable. Specifically, to improve quality, it has become important to polish copper plated substrate surfaces using CMP technology to evenly planarize the surface during a wiring process in the manufacture of a semiconductor device.
It is common knowledge that post-polishing flatness is dependent on wiring density. Subarna Sinha, Jianfeng Luo, and Charles Chiang in “Model Based Layout Pattern Dependent Metal Filling Algorithm for Improved Chip Surface Uniformity in the Copper Process”, Jan. 23, 2007, IEEE, present a technology that maintains the uniformity of wiring densities over an entire layout region by dividing, in a mesh-like pattern, a polished layout region and inserting a dummy into a mesh section having a low wiring density.
Specifically, for example, a wiring density and an edge length of the dummy to be inserted into the mesh are obtained using an equation described in “A Layout Dependent Full-Chip Copper Electroplating Topography Model, ICCAD 2005” by J. Luo, Q. Su, C. Chiang, and J. Kawa. Then, a dummy corresponding to the obtained wiring density and edge length is extracted from a library maintaining plural types of dummies and inserted into an unoccupied region of the mesh. With this configuration, the wiring densities and edge lengths of the respective mesh sections are maintained within constant values and the flatness of the polished substrate surface is improved.
However, according to the conventional art, since wiring layout is not performed with consideration of edge length uniformity, the wire edge lengths of the respective mesh sections after wiring often can be very different from one another. As a result, there has been a problem in that irregularities on the substrate surface after polishing increase, which can deteriorate the performance of the semiconductor device.
Further, as described by Subarna Sinha, et al., in order to uniform the wiring densities and edge lengths of the respective mesh sections, a dummy can be inserted after wiring. However, after the wiring, a library storing dummies for various wiring patterns must be generated. Thus, a problem arises in that the generation of the library results in increased workload as well as increased content stored on a memory.
Meanwhile, although only dummies having typical shapes can be stored, a problem occurs in that an appropriate dummy cannot be inserted and the wiring densities and edge lengths cannot be made uniform, for example, when the wiring density is extremely low and the edge length is extremely great, and when the wiring density and edge length in a mesh after wiring can be in unexpected conditions.